The present invention relates to a liquid crystal display and, in particular, to a display and a display method in which video signals of a plurality of signal standards can be displayed in a similar manner as for multiscan-type displays.
Recently, liquid crystal displays having features such as decreased thickness, lower-voltage operation, and reduced power consumption have been practically applied in place of cathode-ray tube (CRT) displays to personal computers, word processors, color television sets, etc.
A multiscan-type or multisync-type display is a display configured to present images in a plurality of resolutions by a multiscan function (i.e., an automatic frequency follow-up function with synchronization set to various kinds of signals). For example, video signals having resolutions of 640xc3x97400, 640xc3x97480, 1024xc3x97768, and 1120xc3x97750 dots can be displayed as images on a screen of one display. In this connection, xe2x80x9cMULTISYNCxe2x80x9d is a registered trademark of NEC HOME ELECTRONICS (U.S.A.) INC. in accordance with the U.S. trademark registered No. 1,443,951.
Conventionally, when handling input signals of a plurality of signal standards by one liquid crystal display (LCD), there is conducted correction of display positions for fear of positional difference in the vertical and horizontal directions associated with input signals. For example, a control circuit for use with a liquid crystal display has been described in the Japanese Patent Laid-Open Publication No. Hei-3-280084 as shown in FIG. 1.
Referring to FIG. 1, the conventional liquid crystal display controller disclosed by the Japanese Patent Laid-Open Publication No. Hei-3-280084 (to be referred to as conventional example 1 herebelow) includes a vertical synchronization (sync) signal discriminator 71, a horizontal sync signal discriminator 72, a screen mode storage circuit 73, a logical converter for horizontal and vertical sync signals 74, and a liquid crystal controller 75. The vertical sync signal discriminator 71 includes a frequency divider 76 and a latch circuit 77, whereas the horizontal sync signal discriminator 72 includes a divider 78 and a latch circuit 79.
Next, description will be given of operation of the conventional liquid crystal display controller shown in FIG. 1.
A vertical sync signal VS and a horizontal sync signal HS supplied to the controller are fed respectively to the vertical sync signal discriminator 71 and the horizontal sync signal discriminator 72 for decision of  to determine the polarity of each sync signal. For example, when the discriminator 71 or 72 produces a high-level signal, the associated sync signal is assumed to be positive; conversely, when the discriminator 71 or 72 produces a low-level signal, the associated sync signal is assumed to be negative.
Subsequently, the signals created from the discriminating circuits 71 and 72 are delivered to the screen mode storage 73 in the next stage to be supplied therefrom to the logical converter for horizontal and vertical sync signals 74 and liquid crystal controller 75. A horizontal sync signal HS and a vertical sync signal VS outputted from the converter 74 are set respectively to predetermined logical states through signal conversion regardless of a mode of screen operation.
On the other hand, in the liquid crystal controller 75, the received signals are processed for appropriate vertical and horizontal screen positions in each screen mode according to data from the screen mode memory 73. For example, when the horizontal and vertical sync signals HS and VS are assumed to be negative as shown in FIG. 2, the signal currently inputted thereto is judged to be in A mode and hence is automatically displayed in a central portion of the screen of the liquid crystal panel.
In the control operation above, according to the signals obtained by respectively judging the horizontal and vertical sync signals HS and VS, the image can be automatically displayed in the central portion of the screen.
Namely, it is possible to prevent the image from being presented in a portion shifted from the central portion in the screen of the liquid crystal panel.
However, in the method of the prior art, the control operation is accomplished according to two signals, i.e., horizontal and vertical sync signals HS and VS as described above, it is possible to cope with signals in only four modes.
Modifying a portion of the circuit configuration of conventional example 1, a liquid crystal display (LCD) controller of FIG. 3 has been proposed to appropriately correct the display position, for example, in the Japanese Patent Laid-Open Publication No. Hei-3-280085.
The LCD controller of FIG. 3 described in the Japanese Patent Laid-Open No. Hei-3-280085 (to be referred to as conventional example 2 herebelow) includes a vertical sync signal discriminator 81, a circuit to judge relationship between horizontal and vertical sync signals 82, a screen mode circuit 83, a logical converter for horizontal and vertical sync signals 84, and a liquid crystal controller 85.
The vertical sync signal discriminator 81 includes a counter circuit 86 and a latch circuit 87, whereas the relation discriminator 82 includes a delay circuit 88, a gate circuit 89, and a counter 90.
Operation of conventional example 2 will be now described.
A vertical sync signal VS and a horizontal sync signal HS inputted to the system are fed to the vertical sync signal discriminator 81 and the relationship discriminator 82.
The vertical sync signal discriminator 81 is adopted  adapted to decide polarity of the vertical sync signal VS supplied to the system. The operation of the discriminator circuit 81 is the same as that of conventional example 1 and hence description thereof will be unnecessary.
Subsequently, description will be given of the relationship discriminator 82.
In the logical converter 84, the logical state of the vertical sync signal VS is inverted when necessary according to a signal produced from the vertical sync signal discriminator 81 such that a positive-logic vertical sync signal VS is fed to the delay circuit 88. In the delay circuit 88, the vertical sync signal VS is delayed such that a delay sync signal DVS is delivered to the gate circuit 89.
In the gate circuit 89, a logical product is created between the delayed vertical sync signal DVS and the horizontal sync signal HS to resultantly output a logical product signal DVH to the counter 90. In the counter 90, the logical product signal DVH is counted at timing synchronized with the vertical sync signal VS so as to send a resultant signal to the screen mode circuit 83.
In the circuit 83, the value obtained by counting the logical product signal DVH is transformed into a screen mode. For example, when the count of signal DVH is 3, A mode is assumed; whereas, when the count is 2, B mode is assumed as shown in FIG. 4.
When the screen mode is thus decided, a check is carried out to determine whether the horizontal sync signal HS is positive or negative. Consequently, an instruction is supplied to the logical converter 84 to convert the horizontal sync signal into, for example, a horizontal sync signal HS of the positive logic.
In the liquid crystal controller 85, according to data from the screen mode circuit 83 in the same fashion as for conventional example 1, the vertical and horizontal positions are processed in each screen mode. However, in conventional example 2, the screen mode is discriminated as shown in FIG. 10, which is different from the operation of conventional example 1.
In conventional example 2 described above, the screeen  screen mode is automatically detected from the horizontal and vertical sync signals so that the horizontal and vertical positions are automatically set in the screen according to the detected screen mode. That is, the image is presented in the central portion of the screen in an automatic manner. Namely, it is possible to prevent the disadvantage that the image is displayed in a screen area displaced from the central portion.
However, also in the method of example 2, since the control operation is carried out according to two signals, namely, the horizontal and vertical sync signals, it is possible to process the video signals only in four modes like in example 1.
As described above, when handling input signals of plural kinds by one liquid crystal display in the prior art, there can be processed signals in at most four modes. Namely, the upper limit is four modes in the conventional method.
It is therefore an object of the present invention to solve the problem above and to provide a display controller and a display control method for a multiscan liquid crystal display in which even when input video signals of a plurality of signal standards (e.g., five or more kinds of input video signals) are processed by one liquid crystal display to be presented on a screen of an LCD panel thereof, the obtained image can be presented in a central portion of the screen of the LCD panel.
To achive  achieve the object above in accordance with the present invention, there is provided a display controller of a multiscan LCD using an LCD panel including a frequency discriminator means for attaining a mode of horizontal frequency and a mode of vertical frequency of video singnals  signals according to a horizontal sync signal, a vertical sync signal, and a clock signal inputted thereto; a memory circuit means for receiving as an input thereto data outputted from the frequency discriminator means and producing data matching a frequency inputted thereto, and a horizontal timing signal generator means and a vertical timing signal generator means responsive to data from the memory circuit means for arbitrarily setting timing of controlling a display position of the video signals on the LCD panel.
In accordance with the present invention, the frequency discriminator means includes a horizontal sync signal frequency discriminator means for receiving as inputs thereto the horizontal sync signal and the clock signal and a vertical sync signal frequency discriminator means for receiving as inputs thereto the vertical sync signal and the horizontal sync signal. The horizontal sync signal frequency discriminator means includes a pixel counting section including a counter for counting the clock signal for one horizontal period of the horizontal sync signal. The vertical sync signal frequency discriminator means includes a line counting section including a counter for counting the horizontal sync signal for one vertical period of the vertical sync signal.
The horizontal sync signal frequency discriminator means in accordance with the present invention may favorably include a decoder for decoding a horizontal mode according to a count value of the counter.
In accordance with the present invention, the vertical sync signal frequency discriminator means desirably includes a decoder means for decoding a vertical mode according to a counter value of the counter.
Moreover, in accordance with an aspect of the present invention, the horizontal timing generator means includes a fine adjuster circuit means for correcting control data outputted from a memory circuit means in the frequency discriminator means.
Additionally, the vertical timing generator means in accordance with the present invention includes a fine adjuster circuit means for correcting control data outputted from a memory circuit means in the frequency discriminator means.
In accordance with the present invention, the fine adjuster circuit means favorably includes a circuit for achieving an addition or a subtraction between a fine adjustment signal supplied from an external device and an output from the memory circuit means.
Furthermore, in accordance with the present invention, there is provided a display control method for use with a multiscan LCD using an LCD panel. The method includes the steps of attaining, according to a horizontal sync signal, a vertical sync signal, and a clock signal inputted thereto, a frequency mode of the horizontal frequency and a frequency mode of the vertical frequency of video signals; referencing a look-up table according to the frequency modes and obtaining data matching a frequency inputted thereto, and variably controlling, according to the data, generation of a horizontal timing signal and a vertical timing signal determining a display position of the video signals on the LCD panel.
In accordancce  accordance with the present invention, when signals conforming to plural standards including, e.g., video graphics array (VGA) signals in which each array includes (horizontal) 640xc3x97(vertical) 480 pixels, extended graphic array (XGA) signals in which each array includes (horizontal) 1024xc3x97(vertical) 768 pixels, PC98 signals, and MACII signals are inputted to one liquid crystal display, the starting point of displaying a video image can be appropriately established according to a frequency mode obtained from the horizontal and vertical sync signals of the input signals. Consequently, even when the number of dots of the LCD panel of the display is different from that of input video signals for displaying the video image, the image can be presented in the central portion of the display panel.
Furthermore, in accordance with the present invention, a fine adjustment can be accomplished for the output phase by disposing a circuit to conduct, a fine adjustment between the memory circuit and the horizontal and vertical timing generators.
The display controller in accordance with the present invention can be added to the circuit configuration of the conventional LCD without any modifications thereof. This makes it possible to reduce the production cost of the multiscan LCD.